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Engr Ii Design Jobs 2019


ENGR II, DESIGN

Date: 2019-09-17 (New)

Job Description: System hardware board design experience. Analog Circuit Design (Design and Circuit Simulation). Digital Frontend (Low Level design & RTL coding), Verification …

Company: ON Semiconductor
Hiring Organization: ON Semiconductor
Salary: TBD
Location: India
Street Address: TBD

Locality: India
Region: disclosed when applied
Postal code: disclosed when applied


Job Details




ASIC Physical Design Engr, II

Date: 2019-09-17 (New)

Job Description: Experience using Synopsys (ICC/ICC-II ,DC,PT) tools ,Cadence (soce/innovus, RC/genus) design tools. Development of robust ASIC design flow to build & verify…

Company: Synopsys
Hiring Organization: Synopsys
Salary: TBD
Location: Bengaluru, Karnataka
Street Address: TBD

Locality: Bengaluru, Karnataka
Region: disclosed when applied
Postal code: disclosed when applied


Job Details


ASIC/Layout Design Engr, II

Date: 2019-09-17 (New)

Job Description: Experience in Embedded Memory Layout Design & verification using state of the art Cadence Design tools and Calibre, Hercules verification.

Company: Synopsys
Hiring Organization: Synopsys
Salary: TBD
Location: Noida, Uttar Pradesh
Street Address: TBD

Locality: Noida, Uttar Pradesh
Region: disclosed when applied
Postal code: disclosed when applied


Job Details


ASIC Physical Design Engr, II

Date: 2019-09-17 (New)

Job Description: Determines architecture design, logic design, and system simulation. Oversees definition, design, verification, and documentation for ASIC development.

Company: Synopsys
Hiring Organization: Synopsys
Salary: TBD
Location: Noida, Uttar Pradesh
Street Address: TBD

Locality: Noida, Uttar Pradesh
Region: disclosed when applied
Postal code: disclosed when applied


Job Details


ASIC Physical Design Engr, II

Date: 2019-09-17 (New)

Job Description: Determines architecture design, logic design, and system simulation. Oversees definition, design, verification, and documentation for ASIC development.

Company: Synopsys
Hiring Organization: Synopsys
Salary: TBD
Location: Hyderabad, Telangana
Street Address: TBD

Locality: Hyderabad, Telangana
Region: disclosed when applied
Postal code: disclosed when applied


Job Details



ASIC/Layout Design Engr, II

Date: 2019-09-17 (New)

Job Description: Analog and Mixed Signal Layout Design. Knowledge of design for reliability (ie. Our environment is best in class with a full suite of IC design tools…

Company: Synopsys
Hiring Organization: Synopsys
Salary: TBD
Location: Hyderabad, Telangana
Street Address: TBD

Locality: Hyderabad, Telangana
Region: disclosed when applied
Postal code: disclosed when applied


Job Details


Analog Design Engr, II

Date: 2019-09-17 (New)

Job Description: Familiarity with ASIC design flow. DDR I/O Circuit and layout design. CMOS circuit design and layout methodology & flow;

Company: Synopsys
Hiring Organization: Synopsys
Salary: TBD
Location: Bengaluru, Karnataka
Street Address: TBD

Locality: Bengaluru, Karnataka
Region: disclosed when applied
Postal code: disclosed when applied


Job Details


Analog Design Engr, II

Date: 2019-09-17 (New)

Job Description: Knowledge of analog transistor level design in nanometer technologies . Proficiency with one or more IC design CAD packages required.

Company: Synopsys
Hiring Organization: Synopsys
Salary: TBD
Location: Noida, Uttar Pradesh
Street Address: TBD

Locality: Noida, Uttar Pradesh
Region: disclosed when applied
Postal code: disclosed when applied


Job Details


ASIC Digital Design Engr, II

Date: 2019-09-17 (New)

Job Description: Determines architecture design, logic design, test bench design, and test cases. Generates design and verification specifications.

Company: Synopsys
Hiring Organization: Synopsys
Salary: TBD
Location: Bengaluru, Karnataka
Street Address: TBD

Locality: Bengaluru, Karnataka
Region: disclosed when applied
Postal code: disclosed when applied


Job Details


ASIC Digital Design Engr, II

Date: 2019-09-17 (New)

Job Description: Should have very good understanding of Digital Design and various verification methods; Deciding the Verification Architecture and methodology suitable for…

Company: Synopsys
Hiring Organization: Synopsys
Salary: TBD
Location: Noida, Uttar Pradesh
Street Address: TBD

Locality: Noida, Uttar Pradesh
Region: disclosed when applied
Postal code: disclosed when applied


Job Details


ENGR II, CHARACTERIZATION_TL

Date: 2019-09-17 (New)

Job Description: Pixel design and characterization experience; Work with design, Process Integration Engineers, Process Engineering, Fab, and Color Filter Array (CFA)/microlens…

Company: ON Semiconductor
Hiring Organization: ON Semiconductor
Salary: TBD
Location: India
Street Address: TBD

Locality: India
Region: disclosed when applied
Postal code: disclosed when applied


Job Details


Sr MTS Elect Design Engr

Date: 2019-09-17 (New)

Job Description: Hands on experience in Physical Design (floorplan, placement, CTS and routing) and timing closure of complex blocks and Full Chip designs.

Company: Cypress Semiconductor
Hiring Organization: Cypress Semiconductor
Salary: TBD
Location: Bengaluru, Karnataka
Street Address: TBD

Locality: Bengaluru, Karnataka
Region: disclosed when applied
Postal code: disclosed when applied


Job Details


ASIC Physical Design Engr, Sr II

Date: 2019-09-17 (New)

Job Description: Determines architecture design, logic design, and system simulation. Oversees definition, design, verification, and documentation for ASIC development.

Company: Synopsys
Hiring Organization: Synopsys
Salary: TBD
Location: Bengaluru, Karnataka
Street Address: TBD

Locality: Bengaluru, Karnataka
Region: disclosed when applied
Postal code: disclosed when applied


Job Details


Analog Design Engr, Sr II

Date: 2019-09-17 (New)

Job Description: Determines design appro aches and parameters. Familiarity with one or mor e IC design CAD packages required. Analyzes equipment to establish operating data.

Company: Synopsys
Hiring Organization: Synopsys
Salary: TBD
Location: Bengaluru, Karnataka
Street Address: TBD

Locality: Bengaluru, Karnataka
Region: disclosed when applied
Postal code: disclosed when applied


Job Details


ASIC/Layout Design Engr, Sr II

Date: 2019-09-17 (New)

Job Description: Analog Mixed Signal/RF Layout engineer. Expected to have 10 years of relevant experience. Knowledge of custom compiler is preferred.

Company: Synopsys
Hiring Organization: Synopsys
Salary: TBD
Location: Bengaluru, Karnataka
Street Address: TBD

Locality: Bengaluru, Karnataka
Region: disclosed when applied
Postal code: disclosed when applied


Job Details


ASIC/Layout Design Engr, Sr II

Date: 2019-09-17 (New)

Job Description: Experience in leading design activities technically to create differentiating memory IPs. Dense designs, regular style, DFM compliant layout, matching (local…

Company: Synopsys
Hiring Organization: Synopsys
Salary: TBD
Location: Noida, Uttar Pradesh
Street Address: TBD

Locality: Noida, Uttar Pradesh
Region: disclosed when applied
Postal code: disclosed when applied


Job Details


ASIC Physical Design Engr, Sr II

Date: 2019-09-17 (New)

Job Description: Has experience in high performance digital design and CAD, high-speed design, low-power design, high speed clock design and distribution.

Company: Synopsys
Hiring Organization: Synopsys
Salary: TBD
Location: Noida, Uttar Pradesh
Street Address: TBD

Locality: Noida, Uttar Pradesh
Region: disclosed when applied
Postal code: disclosed when applied


Job Details


ASIC Physical Design Engr, Sr II

Date: 2019-09-17 (New)

Job Description: Solid engineering understanding of the underlying concepts of IC design, implementation flows and methodologies for deep submicron design.

Company: Synopsys
Hiring Organization: Synopsys
Salary: TBD
Location: Hyderabad, Telangana
Street Address: TBD

Locality: Hyderabad, Telangana
Region: disclosed when applied
Postal code: disclosed when applied


Job Details


Analog Design Engr, Sr II

Date: 2019-09-17 (New)

Job Description: In depth familiarity with transistor level circuit design - sound CMOS design fundamentals. Familiarity with custom digital design (ie. Aware of ESD issues (ie.

Company: Synopsys
Hiring Organization: Synopsys
Salary: TBD
Location: Hyderabad, Telangana
Street Address: TBD

Locality: Hyderabad, Telangana
Region: disclosed when applied
Postal code: disclosed when applied


Job Details


ASIC Digital Design Engr, Sr II

Date: 2019-09-17 (New)

Job Description: Determines architecture design, logic design, test benchdesign, and test cases. Generates design and verification specifications.

Company: Synopsys
Hiring Organization: Synopsys
Salary: TBD
Location: Bengaluru, Karnataka
Street Address: TBD

Locality: Bengaluru, Karnataka
Region: disclosed when applied
Postal code: disclosed when applied


Job Details


ASIC Digital Design Engr, Sr II

Date: 2019-09-17 (New)

Job Description: The group works on design & verification of digital blocks for High speed serdes ranging from 8G - > 56G. The selected candidate will be working on verifying…

Company: Synopsys
Hiring Organization: Synopsys
Salary: TBD
Location: Hyderabad, Telangana
Street Address: TBD

Locality: Hyderabad, Telangana
Region: disclosed when applied
Postal code: disclosed when applied


Job Details


QA Software Engr II

Date: 2019-09-17 (New)

Job Description: Using software systems design tools and languages. Determines hardware compatibility and/or influences hardware design. Our portfolio spans the following areas:

Company: Micro Focus
Hiring Organization: Micro Focus
Salary: TBD
Location: Bengaluru, Karnataka
Street Address: TBD

Locality: Bengaluru, Karnataka
Region: disclosed when applied
Postal code: disclosed when applied


Job Details


Software Engineer II

Date: 2019-09-17 (New)

Job Description: Responsible for the Design, Development and Support of data warehousing & end-user reporting solutions. Interact with the business users to understand the…

Company: Apps Solutions Inc.
Hiring Organization: Apps Solutions Inc.
Salary: TBD
Location: India
Street Address: TBD

Locality: India
Region: disclosed when applied
Postal code: disclosed when applied


Job Details


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