Jobs in India

Job Description: Create test plan for complex ASICs and drive the DFT implementation. Should have good post silicon DFT bringup and debug experience.

Job Description: Understanding of test compression and ATE debug is a plus. The selected candidate will be a key contributor who is responsible for DFT logic design,…

Job Description: Drive high test coverage through structural and specific IP tests to achieve the quality and DPM objectives. Review the verification plan and drive verification…

Job Description: Prepare silicon debug verification strategy, test plan, and readiness for tester. In this role, you will work closely with various teams within the design…

Job Description: Creates functional tests and corresponding test patterns. Performs diagnosis of test patterns on silicon and optimizes test time.

Job Description: Experience in simulating test vectors. To implement new requirements and incorporate the latest test solutions in the production program to improve the yield,…

Job Description: Tech / M.E/M.Tech in Electronics or related fields. Full-chip DFT working experience with multiple design Tape Outs.

Job Description: Strong DFT knowledge in Scan ATPG, compression techniques and memory test. As a member in our team, you will be responsible for the design and implementation of…

Job Description: Drive Process, test time efficiency and test yield improvement. Meet and maximize Product Functional Test Coverageo Release product test coverage reports, test…

Job Description: Deliver bring-up of test patterns and features post tape-out. Perform CAD development of the design methodology of memory build in self-test (MBIST).

Job Description: Work with verification engineers, stepping in to do run tests when needed. Define test structures, debug structures, and test plans.

Job Description: Qualcomm is looking for an energetic, creative and self-driven engineer to work in Modem , Multimedia , Connectivity , Computer Vision and Image Processing ,…

Job Description: Experience generating test patterns and analyzing and debugging test failures. Define test structures, debug structures, test plans.

Job Description: Validation plan and test development. Monitor test coverage and pattern counts. Top Level Test Pin Planning. Run formal verification between synthesized netlist…

Job Description: Candidate will be responsible for DFT design, RTL coding, DFT verification, Array and logic test development, test vector generation and simulation validation,…

Job Description: Be familiar with SerDes architecture implementation and prepare and implement IP/sub system level Dfx test bench along with relevant test cases (directed /…

Job Description: Develops, tests, and analyzes design automation tools, flows, and methodologies to drive efficiency and optimize PPA for SoC ASIC designs.

Job Description: Collaborating with test engineers to bring up test vectors on test-house/silicon platforms. Communicating with customers to understand their requirements and…

Job Description: Good understanding of Design-for-test(DFT) and logic design is required. Participate in ground breaking Processor design and debug in deep submicron…

Job Description: Experience of debugging test pattern issues. Support the Silicon bringup activities to guarantee highest stability of the test pattern.

Job Description: Cross-Functional Collaboration: Collaborate closely with RTL designers, physical designers, DFT (Design for Test) engineers, and verification teams to resolve…

Job Description: Creates simulation models on their test benches, and documentation analysis findings with minimum guidance. Daily activities will involve working closely with…

Job Description: Knowledge of latest state-of-the-art trends in DFT, test and silicon engineering. Be part of the development organization as an ASIC implementation engineer in…

Job Description: You will be part of the design team driving many facets of DFT for large scale silicon designs. The tasks will include understanding of technical requirements…

Job Description: Desired experience with test constraint generation and working with STA for test mode timing closures. Desired experience with failure diagnostics, silicon…